1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and in particular to a semiconductor device having a redundant circuit and a method of manufacturing the same.
2. Description of the Background Art
In general, semiconductor devices such as an SRAM (Static Random Access Memory) and a DRAM (Dynamic Random Access Memory) are internally provided with redundant circuits. The redundant circuits are provided for the purpose of preventing reduction of yield of the semiconductor devices which may be caused by random defects generating in the process of manufacturing the semiconductor devices. More specifically, the redundant circuit portion is provided as a spare circuit portion having the same function as a specific circuit portion so that the specific circuit portion which has a defect caused during manufacturing may be replaced with the redundant circuit portion to maintain the function of the whole semiconductor device.
Description will not be given on a concept of the structure of the semiconductor device provided with the redundant circuit portion.
FIG. 43 is a plan showing a wafer in which semiconductor devices having conventional redundant circuits are individually formed as chips. FIG. 44 is a plan schematically showing an internal structure of the semiconductor device having the redundant circuit in each chip.
Referring first to FIG. 43, a wafer 1000 is provided with a plurality of chips (semiconductor devices) 500.
Referring to FIG. 44, each chip 500 is provided with blocks N1, N2,. . . , Nm having the same function. For example, each block is formed of a plurality of memory cells having the same function in the semiconductor device.
There are provided a plurality of fuses L1, L2, . . . , Lm which can be blown for deactivating blocks N1, N2, . . . , Nm, respectively. A redundant block S having the same function as the block is formed for replacing deactivated one among blocks N1, N2, . . . , Nm with the same.
A field effect transistor 581 has a gate electrode to which a potential of a ground power supply 579 is applied via a fuse Ls. Thereby, the field effect transistor 581 is maintained at the off state. Therefore, redundant block S is electrically isolated in chip 500.
In order to detect possible defects of blocks N1, N2, . . . , Nm, a pad portion P is provided with pad electrodes 571 and 573 for test.
Function test of the semiconductor device thus constructed will be described below.
More specifically, processing with a laser beam spot, i.e., so-called laser beam trimming (will be merely referred to as "LT") will be described below.
First an electric signal is applied to an unillustrated function tester (will be also referred to merely as "tester") via test pad electrodes 571 and 573 at pad portion P. If chip 500 is normal, an expected signal corresponding to the applied electric signal is output from test pad electrode 573. At this time, normality/failure of chip 500 is determined based on a correlation between the electric signal applied to chip 500 and the output electric signal. If defective block is found among blocks N1, N2, . . . , Nm, the defective block is replaced with redundant block S. Thereby, chip 500 can maintain the originally intended function for making the chip 500 acceptable.
The defective block is replaced with redundant block S in the following manner.
If a defect is detected, for example, in block N1 by the above function test, information relating to fuzes L1 and Ls in chip 500 such as a defect address or position coordinate (i.e., replacement information) in the chip is applied to an LT processing device. This LT processing device radiates a laser beam to a position determined on the basis of the applied replacement information. Thereby, fuses L1 and Ls are fused and removed to isolate the defective block N1 in chip 500.
Since fuse Ls is fused, a voltage of a power supply 575 is applied to the gate electrode of field effect transistor 581 via a resistance 577. Thereby, field effect transistor 581 is turned on, and defective block N1 is replaced with redundant block S.
Description will now be given on a DRAM as an example of the semiconductor device having the redundant circuit described above, and particularly a case where the block having a specific function is a memory cell array.
FIG. 45 schematically shows a conventional structure of a memory cell array of a DRAM. Referring to FIG. 45, a memory cell array 560 includes a plurality of word lines WL extending in the row direction from row decoders 561 via word drivers 563, respectively. A plurality of bit lines BL extend in the column direction from column decoders 565, respectively. Word lines WL and bit lines BL cross each other. Memory cells MC are disposed at crossings of them.
At the outside of word lines WL, a spare word line SWL extends in the row direction from a spare decoder 567 via a spare word driver 569. A spare memory cell SMC is disposed at a crossing of spare word line SWL and each bit line BL.
Spare word line SWL, spare decoder 567 and spare word driver 569 form a so-called redundant circuit.
Then, description will be given on a test of memory circuit characteristics of the DRAM and a method of repairing a defect with the redundant circuit.
FIG. 46 is a plan conceptually showing an example of the redundant circuit in the DRAM. Referring to FIG. 46, a DRAM operation test is first performed, e.g., with a tester to detect a defective bit MC1 in memory cell 560. Then, the LT processing is performed to blow out a fuze FU1 of a word line WL1 containing defective bit MC1, so that defective word line WL1 is isolated from the circuit.
Then, a fuse SFU connected to spare line SWL of the redundant circuit is blown in an appropriate combined manner with the LT processing. Thereby, such a circuit is formed that spare line SWL operates only when an externally applied signal is a signal selecting defective bit MC1.
In this manner, the spare line contained in the redundant circuit is connected to the regular line, whereby the DRAM having the defective portion is repaired to form the acceptable DRAM.
The semiconductor device having the conventional fuses will now be described below.
FIG. 47 is a cross section schematically showing the structure of the conventional semiconductor device. FIG. 48 is a cross section showing a peripheral structure of the fuse in FIG. 47. Referring to FIGS. 47 and 48, an element isolating oxide film 503 having a predetermined configuration is formed at a surface of a semiconductor substrate 501. A plurality of MOS (Metal Oxide Semiconductor) transistors 540 are formed at regions isolated by element isolating oxide film 503.
Each MOS transistor 540 has a pair of source/drain regions 541, a gate insulating film 543 and a gate electrode 545. Paired source/drain regions 541 are formed at the surface of p-type semiconductor substrate 501 with a predetermined space between each other. Source/drain regions 541 have a so-called LDD (Lightly Doped Drain) structure, i.e., a two-layer structure including an n.sup.- -impurity region 541a of a relatively low concentration and an n.sup.+ -impurity region 541b of a relatively high concentration. Gate electrode 545 is formed on a region between paired source/drain regions 541 with a gate insulating film 543 therebetween.
An insulating layer 547 is formed on each gate electrode 545. Side walls of gate electrode 545 are covered with side wall insulating layers 549.
Conductive layers 505 are in contact with source/drain regions 541. Particularly, conductive layer 505 making connection between source/drain regions 541 of different MOS transistors 540 is used as a fuse element.
Each conductive layer 505 other than the fuse element is connected to conductive layers 553a or 553b via plug layers 551a or 551b. Each conductive layers 505 is covered with an insulating film 511 made of a silicon oxide film and formed on p-type semiconductor substrate 501. A hole 511a is formed in insulating layer 511. Hole 511a is located immediately above fuse element 505a, and has a bottom spaced from fuse element 505a by a predetermined distance.
A plurality of aluminum interconnection layers 530 are formed on the surface of insulating layer 511.
Then, description will be given on a method of manufacturing a peripheral structure of the fuse element shown in FIG. 48.
FIGS. 49 and 50 are schematic cross sections showing the peripheral structure of the fuse at one and subsequent steps in the process of manufacturing the conventional semiconductor device. Referring to FIG. 49, insulating layer 503 for element separation and others is formed at the surface of p-type semiconductor substrate 501. Conductive layer 505 which has a predetermined configuration and will form the fuse element is formed on the surface of insulating layer 503. Insulating layer 511 is formed to cover conductive layer 505 forming the fuse element.
Referring to FIG. 50, a resist pattern (not shown) having a predetermined configuration is formed on insulating layer 511. Using this resist pattern as a mask, etching is effected on insulating layer 511. This etching forms hole 511a in insulating layer 511. Hole 511a thus formed is located immediately above conductive layer 505 forming the fuse element, and has the bottom spaced from fuse element 505 spaced by a predetermined distance d.sub.20.
The fuse element is a portion formed on the assumption that it may be cut in a circuit pattern. The cut of the circuit pattern is performed, e.g., by radiation of a laser beam as already described. Now, the LT processing for cutting the circuit pattern by radiation of the laser beam will be specifically described below.
FIGS. 51 and 52 are schematic cross sections showing a peripheral structure of the fuse element at one and subsequent steps in the LT process. Referring first to FIG. 51, when a defective portion is detected in the circuit, a laser beam 20 is radiated to fuse element 505 provided at the redundant circuit through hole 511a. Laser beam 20 passes through insulating layer 511 and reaches fuse element 505.
Referring to FIG. 52, fuse element 505 absorbs the heat generated by laser radiation to melt. When the fuse element is melting, a pressure increases in accordance with rapid increase of a temperature particularly at an upper portion of fuse 505, so that insulating layer 511 located above fuse element 505 is blown off. Thereby, the pressure lowers substantially to the atmospheric pressure, and simultaneously the melted fuse element 505 vaporizes. Thereafter, fragments of fuse element 505 are removed by etching, so that cut of the circuit pattern is completed.
Fuse 505 thus blown is also shown in a perspective view of FIG. 53.
In recent years, there has been tendency that interconnection layers in semiconductor devices are formed of multiple layers for improving density and degree of integration. If the interconnection layers are formed of the multiple layers, interlayer insulating layers insulating the respective interconnection layers have a multi-layer structure. This significantly increases a sum of film thicknesses of the interlayer insulating layers insulating the respective layers. More specifically, a film thickness t.sub.0 of insulating layer 511 shown in FIG. 47 goes to about 20000.ANG..
Meanwhile, film thickness d.sub.20 of insulating layer 511 on fuse element 505a must be substantially 5000.ANG. in order to allow accurate blowing of the fuse with the laser beam. Therefore, it is necessary to provide hole 511a in insulating layer 511 for controlling the film thickness of insulating layer 511 on fuse element 505a.
Meanwhile, insulating layer 511 in the conventional semiconductor device has a very large film thickness of 20000.ANG. due to the multi-layer structure of interconnection layers. Therefore, hole 511a must be deep in order to attain the intended film thickness of insulating layer 511 on fuse element 505a. Therefore, it is difficult to control the depth of hole 511a, resulting in large fluctuation of film thickness d.sub.20 of insulating layer 511 on element 505a.
An amount to be etched can be controlled with an accuracy of, e.g., .+-.10%. Therefore, if an intended depth of hole 511a is 5000.ANG., actually formed hole 511a has the depth from 4500 to 5500.ANG.. Meanwhile, if the intended depth of hole 511a is 15000.ANG., actually formed hole 511a has the depth from 13500 to 16500.ANG.. As described above, although an absolute value of fluctuation is 1000.ANG. if the depth is 5000.ANG., the absolute value of fluctuation goes to a large value of 3000.ANG. if the depth is 15000.ANG.. Further, fluctuation is caused also when forming insulating layer 511. For example, if insulating layer 511 is formed with a fluctuation of .+-.10%, the absolute value of fluctuation goes to 4000.ANG. when the intended film thickness of insulating layer 511 is 20000.ANG., so that the possible fluctuation of film thickness d.sub.20, which is a sum of the fluctuation caused by formation of insulating layer 511 and the absolute value of 3000.ANG. of the above fluctuation caused by the etching, goes up to 7000.ANG..
If the fluctuation of film thickness d.sub.20 of insulating layer 511 is large, following disadvantages are caused. These disadvantages will be specifically described below in connection with individual cases that (1) film thickness d.sub.20 is larger than the intended value and that (2) it is smaller than the intended value.
(1) In the case of large film thickness d.sub.20
(i) FIG. 54 shows a disadvantage caused when film thickness d.sub.20 is larger than the intended thickness. Referring to FIG. 54, when blowing fuse element 505, insulating layer 511 on fuse element 505 is blown off to form a concavity or crater 515. Crater 515 diverges upwardly. Therefore, if insulating layer 511 is thick, crater 515 has a very large open diameter and thus may reach interconnection layer 530. If crater 515 reaches interconnection layer 530, interconnection layer 530 is damaged or broken, resulting in low reliability in electrical connection of the semiconductor device.
(ii) Referring to FIG. 48, insulating layer 511 on fuse element 505 is blown off by the increased pressure of fuse element 505. However, if insulating layer 511 on fuse element 505 is excessively thick, insulating layer 511 cannot be blown off by the increased pressure of fuse element 505 in some cases. In this case, fuse element 505 cannot be cut by melting and removing the same, so that fuse element 505 does not function as the fuse.
(2) In the case of small film thickness d.sub.20
(i) FIG. 55 shows a disadvantage caused when film thickness d.sub.20 is smaller than the intended thickness. Referring to FIG. 55, if film thickness d.sub.20 is excessively small or fuse element 505 is exposed, the energy applied by laser beam 20 is easily taken into ambient air. Therefore, fuse element 505 cannot efficiently store the energy, and thus fuse element 505 is unlikely to melt and vaporize. Therefore, it becomes difficult to blow out fuse element 505, and thus fuse element 505 does not function as fuse.
(ii) If insulating layer 511 has film thickness d.sub.20 of 0 and thus does not cover fuse element 505, fuse elements 505 not to be cut are also blown. This will be described below.
FIG. 56 is a schematic cross section showing several fuse elements exposed through holes. Referring to FIG. 56, one of exposed fuse elements 505 is blown by the laser. The aforementioned etching is performed to remove residue of blown fuse element 505. However, fuse elements 505 other than that blown by the laser are also exposed through insulating layer 511, so that they are simultaneously etched during the etching for removing the residue. As a result, this etching for removing the residue cuts fuse elements 505 not to be blown by the laser.